1. Field of the Invention
The present invention relates to a method of driving a display panel constructed with an array of discharge cells which are display elements having memory capability, and more particularly to a method of driving a plasma display panel (PDP) and also to a plasma display panel and a display apparatus using the same method.
An AC (alternating current) PDP produces a display by light emission while sustaining discharge by applying voltage pulses alternately to a pair of sustain electrodes. The discharge itself completes in one to several microseconds after application of the voltage pulse, but ions, i.e., positive charges generated as a result of the discharge, are accumulated on the surface of an insulating layer overlying the electrode supplied with a negative voltage. On the other hand, electrons, i.e., negative charges generated at the same time, are accumulated on the surface of an insulating layer overlying the electrode supplied with a positive voltage. These accumulated positive and negative charges are called wall charges. Therefore, once the wall charges have been formed by causing a discharge with the application of a high voltage pulse (write pulse), the threshold voltage required to cause a discharge is exceeded by just applying a voltage pulse (sustain discharge pulse) lower than the initial voltage in such a manner as to be superimposed on the accumulated wall charges. That is, the AC PDP has the characteristic that a discharge cell, once subjected to a write discharge with the resulting formation of a wall charge, can be maintained in the discharging state by just applying the sustain discharge pulse alternately in reverse polarity. This is called the memory effect or memory capability. Generally, AC PDPs display images using this memory effect.
2. Description of the Related Art
FIGS. 10 to FIG. 13b show an interlaced plasma display panel (PDP) and a method of driving the same, a patent application on which was already filed by the present applicant (Japanese Patent Application NO. 8-194320).
FIG. 10 is a plan view showing the interlaced PDP. Scan electrodes Y.sub.n and sustain electrodes X.sub.i, extending in parallel to each other, are paired in adjacent positions, each pair forming one display line. On the other hand, address electrodes A.sub.j are arranged intersecting at right angles with the scan electrodes Y.sub.n and sustain electrodes X.sub.i and form a discharge cell in each intersection region. For simplicity, four scan electrodes Y.sub.1 to Y.sub.4, five sustain electrodes X.sub.1 to X.sub.5, and five address electrodes A.sub.1 to A.sub.5 are shown in the figure, but actually, a large number of such electrodes are provided according to the required display resolution. Each discharge cell is spatially decoupled from horizontally adjacent discharge cells by barriers 2 (also called ribs).
Of the sustain electrodes X.sub.i, the odd-numbered electrodes are connected to an X-common driver A, and the even-numbered electrodes are connected to an X-common driver B. In FIG. 10, the X-common driver A is indicated by reference numeral 31, and the X-common driver B by reference numeral 32. The X-common drivers A and B supply pulses such as a blanket write pulse for a reset discharge and a sustain discharge pulse (Vs) to the sustain electrodes X.sub.i. On the other hand, the scan electrodes Y.sub.n are individually connected to Y-scan drivers 4 and are independently driven by the respective Y-scan drivers 4. Of the scan electrodes Y.sub.n, the odd-numbered electrodes Y.sub.2n-1 are connected to a Y-common driver A, and the even-numbered electrodes Y.sub.2n are connected to a Y-common driver B. In FIG. 10, the Y-common driver A is indicated by reference numeral 51, and the Y-common driver B by reference numeral 52. When performing a write discharge in accordance with an input signal, scan pulses (-Vy) to be applied to the respective scan electrodes Y.sub.n are supplied from the respective Y-scan drivers 4, and when performing a sustain discharge for display based on the write discharge, sustain pulses (Vs) to be applied to the respective scan electrodes Y.sub.n are supplied from the Y-common drivers A and B to the scan electrodes Y.sub.n via the respective Y-scan drivers 4. The address electrodes A.sub.j are individually connected to address drivers not shown, and are independently driven by the respective address drivers.
The feature of the above-described interlaced driving method is that the discharge is carried out by utilizing slits (electrode gaps) located on both sides of each of the scan electrodes Y.sub.n. More specifically, in conventional three-electrode, surface-discharge PDPs, the slits used for discharging were predetermined at the beginning, such as the slits between Y.sub.1 and X.sub.1, between Y.sub.2 and X.sub.2, and so on. As a result, to obtain N display lines, a total of N.times.2 electrodes, the scan electrodes Y.sub.n and sustain electrodes X.sub.i combined, were required. This impeded the realization of high-resolution panels. On the other hand, with the above interlaced method, by dividing the X-common driver into two sections A and B it has become possible to supply different signals to the sustain electrodes X.sub.i and X.sub.i+1 located adjacent on both sides of each scan electrode Y.sub.n to which the scan signal is supplied.
When performing discharging in accordance with a video signal, a discharge is caused between the scan electrode Y.sub.n and address electrode A.sub.j by an address signal supplied to the address electrode in synchronism with the scan signal, and using this discharge as a trigger, a discharge is also caused between the scan electrode Y.sub.n and a sustain electrode X.sub.i adjacent thereto, thereby accomplishing the writing. In the interlaced method, one or the other of the two sustain electrodes X.sub.i and X.sub.i+1 adjacent to the scan electrode Y.sub.n can be selected for the discharge to be caused between the scan electrode Y.sub.n and the selected sustain electrode X.sub.i or X.sub.i+1. That is, with the above method, all the slits can be used for discharging, which means that a total of N+1 electrodes, the scan electrodes Y.sub.n and sustain electrodes X.sub.i combined, are required to obtain N display lines. In other words, the number of display lines can be almost doubled while using the same number of electrodes as the previous method.
FIG. 11 is a cross-sectional view showing the above-described interlaced PDP. Discharge space 13 is formed between two glass substrates 11 and 14 disposed opposite each other. The scan electrodes Y.sub.n and sustain electrodes X.sub.i, extending parallel to each other, are formed on the front glass substrate 14; each of these electrodes consists of a transparent electrode 15 and a bus electrode 16. The transparent electrode 15 is formed from indium tin oxide (ITO) or the like, and transmits light reflected from a phosphor not shown. On the other hand, the bus electrode 16 is formed on top of the transparent electrode 15 in order to prevent a voltage drop due to the transparent electrode 15 which has a relatively large resistance compared to an ordinary wiring metal. Since it is opaque, the bus electrode 16 must be formed as a thin line so as not to reduce the display area. These electrodes are covered with a dielectric layer 17.
On the other hand, on the back glass substrate 11 disposed opposite the front glass plate 14 are formed the address electrodes A.sub.j intersecting at right angles with the scan electrodes Y.sub.n and the sustain electrodes X.sub.i. Like the scan electrodes Y.sub.n and sustain electrodes X.sub.i, the address electrodes A.sub.j are also covered with a dielectric layer 12. Though not shown here, phosphors having red, green, and blue light emitting properties are formed covering the address electrodes.
In conventional PDPs, since the slits used for discharging are predetermined, the bus electrode 16 is often formed on one edge of the transparent electrode 15. In the above interlaced PDP, on the other hand, since the slits used for discharging are not predetermined, the bus electrode 16 is disposed approximately in the center of the transparent electrode 15. L1 to L3 indicate the slits. In the figure, the discharge is shown as occurring in the slits L1 and L3, but at the next timing, the discharge occurs in the slit L2; in this way, selective discharging is carried out on all the slits.
FIG. 12 shows a frame structure according to the interlaced method, illustrating one image display frame in the above interlaced PDP. This structure is disclosed in the aforementioned Japanese Patent Application No. 8-194320. The frame structure is based on the "ADS Subfield Method (Japanese Patent Application No. 5-310937)" wherein an address period (A), during which a write discharge is carried out in accordance with display data, and a sustain period (S), during which a sustain discharge (display) is carried out based on the written data, are separated in time, and a gradation display is produced by combining a plurality of differently weighted subfields. In practice, a reset period (R) for initialization is placed before the address period.
One frame is divided into an odd field and an even field, each field consisting of the plurality of subfields (in the illustrated example, the first to the third subfield). In the odd field, for example, the slits L1 and L3 in FIG. 10 are used to produce the display, while in the even field the slit L2 in FIG. 10 is used. In the subfields, the sustain periods are T1, 2T1, and 4T1, respectively, and the sustain discharge is carried out the number of times that is substantially proportional to the length of the period. By selecting the subfields as desired, a display with 8 gray scale levels can be achieved. In like manner, if the number of subfields is set to 8, and the ratio among the sustain periods is chosen to be 1:2:4:8:16:32:64:128, a display with 256 gray scale levels can be achieved. Here, the sustain period ratio need not necessarily be set in a geometric progression manner; rather, more than one subfield may be set with the same number of sustain discharges, or the number of discharges may be adjusted according to the actual display brightness.
FIGS. 13a and 13b are waveform diagrams illustrating the prior art interlaced driving. As stated above, one frame is divided into two portions, an odd field and an even field, each of which is further divided into a plurality of subfields. In the figures, only one subfield is shown from each of the odd and even fields. Each subfield consists of a reset period, an address period, and a sustain period. The reset period is for resetting the wall charges remaining from the immediately preceding subfield, the address period is for performing a write discharge according to display data and thereby accumulating wall charges within designated discharge cells, and the sustain period is for performing a sustain discharge to produce a display in the discharge cells where the wall charges have been accumulated during the address period.
First, the driving for the odd field will be described. In the reset period, a blanket write pulse Vs+Vw is applied to all the sustain electrodes X.sub.i. Since all the scan electrodes are held at ground potential, the potential difference Vs+Vw between the sustain electrodes X.sub.i and scan electrodes Y.sub.n exceeds the discharge initiating voltage between the electrodes, accomplishing the reset discharge between all the electrodes, i.e., in all the slits. At this time, a pulse Vaw is applied to the address electrodes A.sub.j to reduce the potential difference with respect to the sustain electrodes X.sub.i in order to prevent a discharge from occurring between them. As the result of the blanket write discharge in all the slits, excessive wall charges of different polarities are accumulated on the respective electrodes. When all the electrodes are brought to the same potential (in this case, ground potential) after applying the write pulse, the potential difference of the wall charge itself exceeds the discharge initiating voltage, and a self-erase discharge occurs, which neutralizes and erases the wall charge on each electrode.
The address period is further divided into the first half and second half portions. In the first half portion, for example, the odd-numbered scan electrodes Y.sub.2n-1 are scanned in sequence, and in the second half portion, the even-numbered scan electrodes are scanned in sequence. In the first half portion, a scan pulse -Vy is applied in sequence to the scan electrodes Y.sub.2n-1. This scan pulse -Vy is applied in such a manner as to be superimposed on a base pulse -Vsc which is maintained throughout the address period. In synchronism with the scan pulse -Vy, an address pulse (data) Va is selectively applied to the address electrodes A.sub.j, thereby accomplishing the write discharge between the scan electrodes Y.sub.2n-1 and the selected address electrodes A.sub.j. At this time, of the sustain electrodes X.sub.i, only the odd-numbered electrodes X.sub.2i-1 are held at potential Vx throughout the first half period; this makes it possible to specify slits for discharging. That is, the discharge fired by the write discharge occurs only between the scan electrodes Y.sub.2n-1 and the sustain electrodes X.sub.2i-1 supplied with the pulse Vx, and wall charges are accumulated in the discharge cells formed by the scan electrodes Y.sub.2n-1 and the sustain electrodes X.sub.2i-1.
Next, in the second half portion of the address period, the remaining even-numbered scan electrodes Y.sub.2n are scanned in sequence, in synchronism with which the address pulse Va is selectively applied to the address electrodes A.sub.j. At the same time, the pulse Vx is applied only to the even-numbered sustain electrodes X.sub.2i, as a result of which the discharge is selectively caused between the scan electrodes Y.sub.2n and the sustain electrodes X.sub.2i and wall charges are accumulated.
In the sustain period, by applying the sustain discharge pulse Vs alternately to the scan electrodes Y.sub.n and the sustain electrodes Xi, the sustain discharge for display is carried out on the discharge cells where the wall charges have been accumulated during the address period. At this time, in the odd field, the odd-numbered scan electrodes Y.sub.2n-1 and the even-numbered sustain electrodes X.sub.2i, and the even-numbered scan electrodes Y.sub.2n and the odd-numbered sustain electrodes X.sub.2i-1, are respectively maintained in phase, so that a potential difference does not occur in the slits between the respective electrodes and the sustain discharge does not take place in these slits. In this way, in the odd field, the sustain discharge takes place only between the odd-numbered electrodes and between the even-numbered electrodes.
The driving for the subsequent even field will be described next. In the reset period, the same operation as in the first described odd field is performed, likewise accomplishing the reset discharge in all the slits which is followed by the self-erase discharge.
In the address period, on the other hand, in the first half portion the odd-numbered scan electrodes Y.sub.2n-1 are likewise scanned in sequence, but at this time, of the sustain electrodes X.sub.i, the even-numbered sustain electrodes X.sub.2i are held at the potential Vx. As a result, in the even field, the discharge fired by the write discharge occurs only between the odd-numbered scan electrodes Y.sub.2n-1 and even-numbered sustain electrodes X.sub.2i, and wall charges are accumulated in the discharge cells formed by the scan electrodes Y.sub.2n-1 and the sustain electrodes X.sub.2i.
Next, in the second half portion of the address period, the remaining even-numbered scan electrodes Y.sub.2n are scanned in sequence and, at the same time, the pulse Vx is applied only to the odd-numbered sustain electrodes X.sub.2i-1, as a result of which the discharge is selectively caused between the scan electrodes Y.sub.2n and the sustain electrodes X.sub.21-l and wall charges are accumulated.
In the sustain period that follows, the odd-numbered electrodes and the even-numbered electrodes are respectively maintained in phase, so that potential difference does not occur in the slits between the respective electrodes and the sustain discharge does not take place in these slits. In this way, in the even field, sustain discharge takes place only between the odd-numbered electrodes and even-numbered electrodes.
The above driving method, however, has had a problem in that the contrast decreases due to the reset discharge.
It has generally been said that one of the problems facing PDPs is their low contrast compared with CRTs and other display devices. One of the causes for low contrast has been the unwanted light emission caused by the reset discharge. More specifically, in a PDP, the light emission that directly contributes to the display of an image is that caused by the sustain discharge, but on the other hand, discharging during other periods also produces light emission; it has therefore been pointed out that the unwanted light emission by the reset discharge that does not directly contribute to the display of an image contributes to reducing the black level during non-display periods.
It has been confirmed by experiments conducted by the present inventor et al. that when the interlaced method is employed, the contrast tends to further decrease. The cause has been the discharge that occurs in all the slits during the reset period. That is, in the odd field, the slits between the odd-numbered electrodes and the slits between the even-numbered electrodes are actually subjected to sustain discharge, but the reset discharge is also performed on the remaining slits. Likewise, in the even field, the slits between the odd-numbered electrodes and even-numbered electrodes are actually subjected to sustain discharge, but the reset discharge is also performed on the remaining slits. As a result, in the interlaced method, the reset discharge is performed twice on each slit, once each in the odd field and in the even field. In non-interlaced PDPs, reset discharge is performed once on each line in one subfield; therefore, by simple comparison, the number of reset discharges is doubled. This has been a serious problem faced by the interlaced method intended for a high-resolution panel.